As VLSI technology scales, interconnects are becoming the dominant factor in determining system performance and power dissipation. Interconnect reliability due to electro-migration and electromagnetic interference compliance (EMC) have become serious design issues particularly for long signal lines. In fact, it has been shown that interconnect Joule heating in advanced technology nodes may strongly impact the magnitude of the maximum temperature of the global lines despite negligible changes in chip power density which will, in turn, strongly affect the electro-migration lifetime of the interconnect. In analog designs, unidirectional current flow and smaller wire geometries also raise EM concerns for the signal nets. Behaviors of analog circuits are even more sensitive to layout induced parasitics and thus electro-migration concerns due to the unidirectional current flows in various circuit components. Parasitics not only influence the circuit performance but may often render it non-functional.
In addition to the increasing concerns about electro-migration, voltage drop, also called IR drop, represents another class of challenges for modern electronic circuits. Voltage drop represents the voltage reduction that occurs on power supply networks. The IR drop may be static or dynamic and results from the existence of non-ideal elements—the resistance within the power and ground supply wiring and the capacitance between them. While static voltage drop considers only the average currents, dynamic voltage drop considers current waveforms within clock cycles and has an RC transient behavior. Similar effects may be found in ground wiring, usually referred as ground bounce, whereby current flows back to the ground/Vss pins causing its voltage to fluctuate. Both effects contribute to lower operating voltages within devices (e.g., logic cells/gates in digital circuits), which in general increases the overall time response of a device and might cause operational failures due to heat dissipation.
Conventional steady-state or transient thermal analyses use time consuming time-stepping or domain discretization algorithms such as finite element methods or finite difference methods on discretized designs. Moreover, these conventional steady-state or transient thermal analyses are often after-the-fact in that these analyses are usually performed after electronic designs are completed at, for example, the block level, the chip level, the package level, or even the board level at which integrated circuit blocks are integrated with a printed circuit board. The limitations on the sizes of time-step and the amount of computation time as well as intensive computation have rendered transient thermal analyses less than desired.
The recent advent of mobile communication and computing devices that encapsulate high-powered electronic devices in an enclosed or semi-enclosed enclosure further exacerbates the concerns about heat dissipation and thus emphasizes the importance of correct characterizing the thermal behavior of electronic devices, especially during the early stages of the design cycle. Conventional approaches often adopt the conjugate thermal analysis approach that iterates between the heat transfer equation for the solid (the electronic design) and the differential or partial differential equations of computation fluid dynamics and thus consume large amounts of computational resources in addition to other shortcomings.
Given the advantages provided by various techniques described herein and disadvantages in the conventional approaches, there exists a need for effective and efficient techniques for implementing electronic designs with thermal analyses of the electronic design and the surrounding medium.